CAD View Generation and Verification of Digital Hard IPs

Abstract

The topic “CAD View Generation and Verification of Digital Hard IPs" is solely oriented towards the process of SoC (System on Chip) manufacturing. A SoC consists of multiple IPs (Intellectual Property) and additional circuitry on a single-silicon die. In Digital design flow of SoC manufacturing, the role of CAD View Generation is to generate various views for different IPs, which will be used in that SoC, in a structured format so that it could be the best possible input database (collection of di_erent views) for various steps of design flow like floor-planning, PnR (Placement & routing) etc. Various Backend and Frontend tools are used in generation of these CAD Views. Some views we get as input, using those input views (raw data), a complete structured package has to be prepared. To generate liberty views, TIMEX and IPGEN tools are used jointly. Some views are derived from the basic views by using Virtuoso and Milkyway tools. When all the required views are generated for Floor-planning and PnR purposes, then the package comes under the 10th Maturity level (MAT10). So, before a MAT-10 IP package is delivered to PnR team, it has to pass through number of checks in the verification process, where all the views are checked and verified with the help of IPSRCEEN tool.