Power Estimation and Analysis of Integrated Graphics SoC

Abstract

VLSI industries are moving to low power designs due high demand of mobile devices. So to design a compact gadget one of the key parameter is to reduce power consumption. This thesis explains the Intel methodology for power estimation which is used to find out power dissipation for different types of simulations on a design at different levels of hierarchy. Power Estimation is a methodology used to optimize the power consumption at different stages of design by analyzing power reports. Power report generation flow is discussed which uses IC complier with some stcl and perl script to generate data. Analysis of power reports includes finding out major power consuming area, scope for power reduction and evaluating the performance which helps to build a power efficient design. Power saving techniques like clock gating, frequency and dynamic voltage scaling and power gating are explained. Multi Bit conversion is one of the best power reduction technique to reduce power as well as area required for design is also discussed. DOP downsizing is one of the traditional technique widely used for power reduction but in graphics design it results only 0.01% of reduction in total power. DOP toggle rate mismatch issue is discussed with its solution. A tool called power artist has been described which is used at an initial phase of the design for power reduction is described. This tool proposed with simulation results having 10% improvement in total clock gate efficiency with respect to other tools. Pulsed latch based design which is the latest technique to reduce power is implemented and it reduces approximately 10% overall power. The methodology to implement pulse latch with its pros and cons is described. Future scope for power reduction in design is also discussed.