High-speed Subsystem IP Verification

Abstract

SoC (Systems-on-Chip) is integration of various subsystem IPs(Intellectual Property). Integration requires interfaces. Today’s interfaces are high-speed interfaces, to full-fill the requirement of high speed data transfer. To make SoC bug free, it is important to integrate and verify the various functionality of high speed subsystem interface. To achieve this IP level verification performed and then SoC level verification performed to assure that subsystem IP is working correctly in SoC. In this project constraint random verification technology is used to verify the subsystem and to find maximum bug form it. For the Subsystem Verification the LVP (Lightweight Virtual platform) and VAL(Verification Abstraction layer) based verification environment is used. The LVP (SystemC and Transaction Level Modeling based Light Weight Virtual Platform) is used in Subsystem Verification. The main purpose of LVP is to provide a preliminary platform which contains minimum components and it permits to run test and allow to plug the RTL IP, VIP(Verification IP). ARM Cortex R4 processor is main component in LVP. A wrapper of SystemC around the Cortex R4 Fast Model is created with TAC(Transaction Accurate Channel). The virtual platform could be used as a subsystem in the verification environment. A verilog wrapper is provided of the virtual platform and various master/slave interfaces are exposed to be integrated with IP components or VIP components. The VIP is reusable module in verification environment which contains of functional coverage, traffic generators, BFM(Bus Functional Model), protocol monitors blocks. VIP increase the development of a total verification environment to reduce the time to verify the IP. High speed interfaces are very important for new generation SoC. The verification platform for High speed USB 2.0 is developed using SV-UVM(System VerilogUniversal Verification Methodology). The test cases for the same is developed in C. Various bugs are found and resolved as a result verification is achieve upto 78%.