Automatic RTL Generation of FIR Poly-phase Decimation Filter

Abstract

Decimation is the most element of Delta-Sigma ADC chain in a Digital Signal Pro-cessing (DSP) system. Decimation is used to reduce the sampling rate by retaining every kth sample. So, the motivation to design decimation filter is to reduce the cost of processing in terms of computation, area and power. A Direct form FIR decimation filter is decomposed into contemporary poly-phase structure and requires smaller sub filter which operates at lower sampling rate. Multiply and Accumulator Unit (MAC) and a delay chain can be used to replace the sub filter. So, poly-phase structure avoids the redundant calculation for computing the output and eliminates use of any memory inside the sub filter, at their inputs or at the out- put except the MACs. A simple change in co-efficient selection and number of input cycle rendered to each MAC for computation will reconfigure the entire structure to operate as variable rate decimation filter.