Electrical Characterization of Analog Intellectual Properties Embedded in System on Chip

Abstract

The rapid advancement of semiconductor process technology to sub-micron dimension has led to the development of broad spectrum of integrated circuit (IC) system components. These complex system components are being further integrated on silicon to form larger System on Chip (SOC). However, this same process technology is defined by smaller and more delicate structures that must interface and communicate with the harsh external world with voltages and currents that will easily damage and destroy the IC. Designing and validating the products at this edge technology is becoming challenging. Validation is a very crucial phase of today’s design and manufacturing process, which takes more time as the products moving towards cutting edge technologies and high frequencies. Validation is responsible for ensuring that products meet applicable industry specifications, end-user expectations and business. This thesis describes the validation flow of different analog Intellectual Property (IP). The different Analog IPs are validated in order to check their functionality at various conditions. It has been a major focus of research and development since it is the vital stage of product life cycle.