Design And Characterization Of Memory Compiler And Enhancing Bitcell Performance With CNTFET For IOT Applications

Abstract

Internet of things is the wave of transformation for manufacturers. Chips used for IOT applications will spend their most of the time in sleep mode, waking up occasionally to execute some task. So leakage in deep sleep mode is very critical. This needs ultra-low power devices. Trade-off between area, speed and low power is the main design challenge. Today the devices where SRAMs are used need it for either its high-speed or its low power consumption, but not both. So the demands driven by IOT needs an evolution of existing technology. SRAMs need to be evolved in such a way that a customer needs not worry about the trade-off between power and performance. New techniques like write assist and read assist are required to improve the performance of SRAM memory compiler. These techniques make SRAM writable at lower voltage with ensured read stability. But speed and area of memory compiler are affected with implementation of assist techniques. Also the main responsible component for speed and leakage in memory is bitcell. So by implementing and comparing carbon nanotube technology with CMOS technology, I came with the result that CNTFET can solve the tradeoff faced by IOT applications. Here input, output characteristics, variation effects, on-off currents for MOSFET and CNTFET are compared which shows better performance of CNTFET. In SRAM memory compiler, 6T CNTFET SRAM bitcell is designed and the bitcell performance of CNTFET 6T SRAM cell is analyzed. It shows that it gives the better performance with improved read, write operations without any assist circuits. Also it proves to be the better candidate for bitcell in terms of PPPA - Static Power, Dynamic Power, Performance and Area.