Study of Electro-migration (EM) on Full Custom VLSI SRAM Designs and Development of an EM Assessment Methodology for Memory Compilers

Abstract

With each progressing technology node, the devices are scaled down to improve the performance and can be densely packed in comparatively smaller area. The active devices are getting better due to scaling but at the same time the passive components like interconnects are getting worse. That is because as the number of devices are increasing in smaller areas of ICs, the number of metal interconnects, their length and their stacks are increasing resulting in more complex and congested routing. Hence the problems like electro migration (EM), IR drop and crosstalk are magnified for the technology node below 0.1um which were not that much significant for the technology above the 0.1 um. The IR drop is causing the voltage to drop significantly in the interconnects itself such that the devices will not have enough supply voltage to function correctly hence causing the functional failure instantly while the EM may cause the interconnects to short or open eventually after the IC is functional for sufficient long time. So the EM is issue regarding the reliability of the whole IC, because the failure of one of interconnects may cause the whole IC to fail. In today's era, nearly 70\% of the chip area is occupied by the memory itself. So it is very important that the designer have the knowledge of the severity of the EM on the memories when designing the IC and it is therefore recommended to consider the electro migration aware physical design at the design stage itself. In this project the objective is to develop the methodology to predict the worst case EM violation of the power nets in any given memory instance of the specific memory compiler. The purpose of reporting the worst case EM violation is that this is the highest EM violation and all the other violations will be less severe than this one on the memory instance. The designer need to solve for the worst violation first before going to the next EM violation. The phenomenon of electro migration and the factors affecting the same is studied first. Then the tools required for the EM analysis is understood and used to generate the power EM violation data as the benchmark data. I have selected the single port low leakage type of SRAM memory compiler in 28nm FD-SOI technology. Finally, power EM assessment methodology is proposed to estimate EM violation in a memory instance based on its physical characteristics.