Automation of Design Flow for Efficient Implementation of Latch Repeater Functional Blocks in Custom Design Approach

Abstract

Modern ASIC designs having ultra-deep submicron processes, have interconnects which are very long. RC delay on such interconnects are so large that data on these paths require multiple clock cycles to reach destination. Logically we have sufficient sequential stages on such interconnect paths, so that it’s only matter of splitting the RC delay between sequential stages to solve them. Retiming is the methodology used to split the interconnect delay between one of more sequential stages by adding or changing placement of sequential elements. This retiming can solve the paths with more than one cycle of interconnect delay between them. The sequential element is referred to as a latch repeater. Our goal is to place group of these latch repeaters in one functional block such that they are aligned to their input and output nets, results in optimal interconnect and latch/FF implementation. In the existing mode of work, the input and output interconnects may be routed independently, resulting into possibility of misalignment with latch repeater location, and hence sub-optimal design. The work details a flow, in which input and output net pairs are found by doing synthesis of RTL code and using scripts to parse logic cone by which we find input output relationship across the sequential. Next step is to obtain open length between this two nets and reduce it to a value as small as possible. Open length is defined as total of misalignment in horizontal and vertical direction between end points of given two nets. Data obtained from this two steps is used to implement the functional blocks which contains sequential.