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DC Field | Value | Language |
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dc.contributor.author | Shelat, Malav | - |
dc.date.accessioned | 2015-08-11T08:02:20Z | - |
dc.date.available | 2015-08-11T08:02:20Z | - |
dc.date.issued | 2015-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/5965 | - |
dc.description.abstract | New generation 64 bit microprocessors are penetrating from embedded systems to server systems. For such a large system, architecture validation is important. For multiple versions of such architecture to be implemented, Architecture Validation Kit (AVK) is required. AVK is a product of ARM to ensure compliance of architectural technology features and rules. Every ARM architecture licensee intending to release ARM compliance chip, needs to ensure that their implementation complies with features specified in ARM Architecture Reference Manual (ARM ARM). As the ARM ARM is just a manual and does not check for compliance, the AVK is released along with this for compliance validation. AVK is a set of test suites to check different parts of the ARM architecture. These suites qualify if a specific implementation complies with behavior as specified in ARM ARM. The ARMv8-A architecture is the next generation ARM architecture targeted at the Applications Profile. ARMv8 is used to describe the overall architecture and encompasses two register width states, AArch64 and AArch32 which are used to describe execution with 64-bit wide general purpose registers and 32-bit wide general purpose registers, respectively. The ARMv8 architecture permits the execution of different software layers - such an Application, an Operating System Kernel or a Hypervisor using either AArch32 or AArch64, and the architecture defines how the execution in AArch32 and AArch64 interact. ARMv8 architecture supports the capability to have interprocessing between AArch32 and AArch64 operation. The work carried out improved efficiency and effectiveness of Interprocessing (IP) verification of AArch32 features described in ARMv7 architecture, Verification of the AArch32 Long descriptor translation table format with and without virtualization extensions, needed for compliance testing of ARMv8-A architecture based implementations. The mechanism implemented optimizes number of test cases/simulations needed for compliance testing of ARMv8-A class CPUs in above areas. Optimization of simulations ranges from 25% to 75% for various suites. By using this optimization, it brings down the support cost, compute resources and improves the overall quality of the AVK product. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 13MECV09; | - |
dc.subject | EC 2013 | en_US |
dc.subject | Project Report | en_US |
dc.subject | Project Report 2013 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2013 | en_US |
dc.subject | 13MEC | en_US |
dc.subject | 13MECV | en_US |
dc.subject | 13MECV09 | en_US |
dc.title | Improving Efficiency and Effectiveness of IP and AArch32 Compliance Verification for v8-A CPUs | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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13MECV09.pdf | 13MECV09 | 2.46 MB | Adobe PDF | ![]() View/Open |
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