Modeling and Verification of Power Aware IO Models

Abstract

Today's increasingly complex SoCs are typically used in portable systems that must also support increasingly longer battery life and therefore must minimize power consumption. Even non-portable systems must avoid wasting energy, to minimize both power and cooling costs. In both cases, active power management is required to ensure energy efficiency. Although active power management enables the design of low power chips and systems, it also creates many new verification challenges. For portable devices which can offer greater functionality and performance at lower costs and smaller sizes, System-on-Chip (SoC) needs to be very efficient. Power efficiency has become one of the biggest concerns in the designing of complex SoCs. For example, as more transistors are integrated onto a single chip, the power density increases rapidly. Excessive power consumption can overheat and eventually burn out the entire device, though a higher voltage supply can make devices work faster due to the limited battery life by heating issues, voltage is scaled with technology. Therefore, balancing both power and performance has become a critical design requirement. Macros are designed to operate in multiple low power modes depending upon the voltage value of each supply. A single SoC has various mixed signal design components which are designed using various low power techniques like DVFS(Dynamic Voltage and Frequency Scaling), retention, standby,multi-power domain etc. For these blocks to operate correctly on silicon, power related behaviour must be known at early design flow. Power Aware simulations have been recently in use for simulating and verifying these low power features at the RTL level. It gave a good confidence in the maturity of the power management module.