Margin Analysis of Memory Compiler for FinFET Technology

Abstract

The memory content of System-on-Chip (SoC) designs has increased dramatically over the past few years. More and more silicon area consists of memories with different functionality in the forms of embedded SRAM, ROM, and multi-port register files, just to name a few. In present day scenario SOCs due to need of area optimization SOC designers want to have a memory of different sizes and with different aspect ratio as per other logic circuitry. Memory compilers provide a powerful dashboard of options that enables System-on-Chip (SoC) designers to explore trade-offs between performance, area, power, and statistical yield to generate optimal memory configurations. This dashboard control capability is critical at lower technology nodes where design and process complexities require sophisticated management of the various trade-offs to effectively meet stringent end-product requirements and increasingly narrow time to market windows. The underlying transistor technology most SoCs are built on today uses the planar MOSFET transistor. One of the major challenges with scaling planar MOSFETs over recent process technology generations has been in delivering on the switching speeds in large SoCs at reduced power consumption levels. One of the key limitations impacting power in planar MOSFET is the short channel effects and in particular the off-state leakage current which increases the idle power unnecessarily. The semiconductor industry has been very innovative finding ways to minimize the shortcomings of planar FETs over recent process generations, while seeking a strong alternative. Finally, a viable solution has emerged, the FinFET. This evolution of the MOSFET has proven to be the best choice for next generation processes but brings with it some new challenges for manufacturing and design that require careful consideration if the benefits with FinFETs can be capitalized on. To make the optimization of timing requirement for all the instances generated of different configuration different methods like self-timing are used in the memory compiler. This project gives the solution for timing optimization for every memory instance generated from memory compiler by the use of self-timing circuit. In the initial phase of the memory compiler development, various kind of analysis is done on the models provided by the foundry to decide the behavior of the models in terms of timing, power and leakage. Bit cell and logic are the two kinds of models which foundry provide for memory design. Bit cell design is provided by foundry and memory designers are allowed to do very small changes in the Bit cell design. Most of the effort in the memory design is in the periphery design which is made up of logic models and this is the main reason to do the logic model analysis. During the earlier phase of the periphery design, designer keeps some margins in the design to compensate the variations due to mismatch in the devices. In this project we will analyze various margins like read margin, write margin, logic margin, for SRAM memory at FinFET technology node.