Development of Verification IP for CAN Controller Using UVM

Abstract

In SoC the time-to-market and manufacturing yield schedules are very crucial, so it is required that the verification process and analysis solution provide best performance. The verification techniques should be such that it reduces verification time and iteration time in design, if any bug is found in design. The UVM class library has built in verification components which can be used to quickly develop reusable and well-constructed verification environment using system verilog. The thesis work describes development of verification IP for CAN controller using UVM methodology for SoC verification. The Controller Area Network is asynchronous serial bus network that connect devices, sensors, and actuators for control applications. It supports multimaster communication for automotive application. UVM class library provides much automation to system verilog language. There are number of macros which provide automation for sequence and data automation features like print, copy, compare which increases the automation and time required in verification. Earlier verification methodology was developed independently by different vendors but UVM is an accellera standard which is supported by multiple vendors like Cadence, Mentor graphics, Synopsys. Sequence library is developed which is used to provide transaction to driver. Using sequence library even random transaction can be generated and thus corner cases can even be verified. The driver is implemented which is used to drive the design at signal level, using transaction provided by sequence. The monitor is developed which resembles real time slaves present on CAN bus, which monitors the Tx line of design and store the message frame in transaction which is broadcasted to scoreboard for automatic checking. Verification IP also includes wrapper which is used to plug the VIP at SoC level environment. Testcases are developed in C which is used to configure the registers in CAN controller and synchronization is done between C side test and SV side test. Verification IP developed should be compatible for all test scenarios. Various test scenarios of CAN controller is also verified in this work.