Validation Of Unified Power Format and Low Power Features

Abstract

Increasing functionality of battery operated devices challenge power as a key design metric along with area and timing. While dynamic power played a major role for power dissipation until now, with technology shrinking static power is equally important. Designers are using different techniques to improve power dissipation. With increasing complexity of devices, it is must essential to use EDA (Electronic Design Automation) tools. Design houses are widely using tools from EDA vendors rather than making their own. EDA companies are challenged enough to improve on algorithms for better optimizations on power, area or timing. They are adding more and more features to make designs more better. With the advent of Unified Power Format, designers are using UPF to provide power intent separated from the design functionality in RTL. So with this increasing complexity and functionality of different tools, it is must require to validate tools properly with different scenarios. If anything missed during validation, it will create an issue during design phase and it will impact on chip quality. To validate different features, it must require some base design on which experiments can be done. With a goal to create a reference design for low power validation, the thesis work covers aspects of creating UPFs with UPF 1.0 standard for different partitions. Different design phases like synthesis, floorplaning, placement, Clock Tree Synthesis (CTS), routing, power calculation are done on this design. This design will be used to experiment different low power experiments and EDA updates from multiple vendors. Also this design will be used to test flows which are developed on top of tools for low power activities. It is mentioned above designers are using UPF to provide power intent file. It is IEEE standard. Designers are using UPF 1.0 standard. But latest IEEE standard for low power is UPF 2.x. It has some enhancements from UPF 1.0 standard. Major enhancement is supply sets, isolation strategy and power state table. As second step of this project, it covers conversion of UPF 1.0 to UPF 2.0 with same power intent and validate UPF 2.0 constructs. One partition from reference design is used for UPF 2.0 validation. Different scenarios are made in UPF to validate different tools. This UPF is passed through different tools starting from low power lint checking to synthesis, P\&R tool, formal equivalence tool and power calculation tool. Some of issues captured with behaviour of tools with UPF 2.0.