Development of Verification Environment for Behavioural Models of Analog Mixed Signal IP PLL

Abstract

To accomplish the design chip of an integrated circuit, the first step is to know the design specification. The next step is to make a behavioural model of that design and then this behavioural design is converted to a RTL description with the help of synthesis tools. This is the basic building block of any RTL to GDS flow. There are some designs which are not synthesizable. These designs are basically analog models. Therefore there is no RTL description written for these designs. Transistor level net-list is provided for the complete verification of any SoC. The accuracy of the verification from SPICE tools is very high but with that the time requirement is also huge. Therefore only behavioural models are made for analog designs so that the verification for SoC can be done with a less amount of time. When the behavioural description is written in a HDL language then the equivalence checking is done between behavioural description and transistor level net-list.

Phase Locked Loops (PLLs) are electronic circuits used for frequency control. For every SoC, basic clock generation circuit is required. PLL is an analog IP which is not synthesizable. Modelling and verifying analog designs in behavioural way such that the time requirements for making the design and also to verify that can be reduced. There are different types of PLL designed but the basic functionality is same for all. Making of a generic test bench for all the types or PLL can reduce a huge time also with all the tests applied to the PLL. This technique can be used effectively by the help of scripts.