Implementation of a Five-Level Inverter Scheme using Advanced Tool with Emphasis on DC-Link Capacitor Voltage Balancing

Abstract

Multi-Level inverter (MLI) is widely used for medium-voltage and high-power applications; as the number of level increases, rating of power semiconductor devices, switching frequency and the harmonic content in an inverter output voltage waveform reduces. In MLI, neutral-point clamped (NPC) inverter is widely used for inherent advantages offered by it amongst other inverters. There are different modulation methods for generating the gate pulses for switches (IGBTs) of diode clamped inverter or neutral-point clamped inverter. Amongst these, carrier based pulse width modulation (CBPWM) are used widely for switching of multi-level inverter due to their simplicity, flexibility and reduced computational requirements compared to space vector pulse width modulation (SVPWM) technique. The main drawback of NPC inverter is the fluctuation in the neutral-point voltage and the corresponding imbalance is created in dc-link capacitor voltages. In this five-level NPC inverter for switching phase disposition pulse width modulation (PDPWM) technique is used. The balancing scheme is proposed for five-level inverter by providing offset in the individual carriers without any extra hardware. In this scheme, only capacitor voltages are measured and not the load current. A band is set and capacitor voltage is allowed to vary between that band and hence capacitor voltages remain almost constant. When capacitor voltage touches upper band, the offset which will discharge the capacitor and bring the voltage back within the band is provided and when capacitor voltage touches lower band, the offset which will charge the capacitor and bring the voltage back within the band is provided. In this proposed control strategy, the dc-link capacitor voltages are balanced for five-level NPC inverter with 2 hp squirrel-cage induction motor connected as a load. However, the limitation of this control scheme is the fundamental output voltage of an inverter is not as per the requirement. The output voltage has full dc-link voltage but waveform has only three-levels when machine is operated in five-level. The quarter-wave symmetry in an inverter output voltage is lost so harmonics in the output voltage waveform increases compared to sinusoidal pulse width modulation (SPWM) technique for the same level. When modulation index (Ma) is 0.96 i.e. motor is operating in five-level, the THD in the line voltage at an inverter output is 20.41 %, rms line voltage is 222.8 V when dc-link voltage is 400 V, which is slightly less than that of an ideal NPC inverter. This will affect V/f ratio as well as torque of the motor. Also, dv/dt stress on switches increases due to less number of levels compared to ideal five-level NPC inverter. The simulation is carried out in MATLAB/Simulink. The simulation model is integrated with the dSPACE DS1104 controller board to generate gate pulses to drive five-level NPC inverter in an open-loop.