Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/6197
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kansara, Jaydip | - |
dc.date.accessioned | 2015-09-22T12:04:52Z | - |
dc.date.available | 2015-09-22T12:04:52Z | - |
dc.date.issued | 2015-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/6197 | - |
dc.description.abstract | The project ESL Validation of Ethernet Switch aims at validating the multiple fea- tures of the switch used in the data center environment.These features include the data link layer, network layer and overylay network features of Ethernet switch. Results are compared with the expected result of the correct behavior of the switch.Bugs which are found during the validation are reported back to the software model of the switch to obtain the bug free Register Transfer Level(RTL) implementation. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 13MCEC07; | - |
dc.subject | Computer 2013 | en_US |
dc.subject | Project Report 2013 | en_US |
dc.subject | Computer Project Report | en_US |
dc.subject | Project Report | en_US |
dc.subject | 13MCE | en_US |
dc.subject | 13MCEC | en_US |
dc.subject | 13MCEC07 | en_US |
dc.title | Electronic System Level Validation Of Ethernet Switch | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, CE |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
13MCEC07.pdf | 13MCEC07 | 2.42 MB | Adobe PDF | ![]() View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.