Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6268
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dc.contributor.authorPatanwadia, Krunal-
dc.date.accessioned2015-10-06T04:37:30Z-
dc.date.available2015-10-06T04:37:30Z-
dc.date.issued2015-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/6268-
dc.description.abstractWe automate the flow of memory generate for the user. User provides set of configuration on basis of that we build a product for them. We work on different technology such as 14nm, 28nm, 45nm etc. Within each technology we have different compilers such as ROM, Hiperf RAM, Loleak RAM etc. and for each compiler we generate different cuts.Cut mean Configuration for single memory. We can generate this memory (product) in two ways: 1) Layout view. 2) Netlist view. Here we will mainly focus on Layout view. How the whole process follows to generate a product. We will see two approaches to generate memory and see how time is saved. We will generate cuts by using basic cells and generate whole memory as per User’s requirement. Once the product is created we have to validate this product and for validation we have to run the simulation on all possible different cuts where input option changes.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries13MCEN08;-
dc.subjectComputer 2013en_US
dc.subjectProject Report 2013en_US
dc.subjectComputer Project Reporten_US
dc.subjectProject Reporten_US
dc.subject13MCENen_US
dc.subject13MCEN08en_US
dc.subjectNTen_US
dc.subjectNT 2013en_US
dc.subjectCE (NT)en_US
dc.titleAutomation and Optimization in Memory Generatorsen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, CE (NT)

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