Development & Verification of Standard Cell

Abstract

ASIC(Application specific Integrated Circuit) must be optimized in terms of leakage power and delay. This report will explain standard cell optimization method used by company to get optimized cost product, which will be power delay product (power x delay) in most of the cases. It gives detailed explanation of different input files used for tuning by celltuner tool, which is used to perform sizing on the standard cell. Company has decided to keep flat schematic in the source for each cell used in project so far. So we need to convert all hierarchical schematics to flattened ones which will not have any ARM internal symbols and everything will be defined in terms of NMOS and PMOS models provided by foundry. This report explains how we can use Prosizer tool for this purpose and also for schematic sizing. Pretty unfied builders is the project to reduce the effort required to configure DARBuilder, CellBuilder and QABuilder for an entire Standard Cell (SC) platform. The goal is to have a minimal collection of "source" files which can be used "as is" for all the automated phases (ie builders) of a SC flow and all products in a particular platform. Various Cell level Physical checks and Electrical Checks are performed to estimate changes in Standard Cell Library. Device failing on silicon is more risky than on design. So by providing a margin of failure various Electrical Checks : Flop Margin Analysis, Balanced Beta Ratio, Latch Node Stability, Level Shifter Analysis, Electro-Migration are performed and the design is allowed to operate under various PVT (Process ,Voltage & Temperature) conditions to ensure under what conditions design can withstand. For these a flow named “EDAR“ (Electrical Design Assurance Report) is developed by company. The report explains how we can use DARBuilder Tool for this purpose.