Improvement in Error Resilience for Compressed VLSI Test Data using Hamming Code based Technique

Abstract

In the current scenario of IP core based SoC, to reduce the test time and test cost, the test data is preprocessed and compressed heavily. This compressed test data are transferred from Automatic Test Equipment (ATE) to chip under test through a serial communication link and will be decompressed on-chip before applying to actual DUT. If there is a problem with this link, there may be a flip in bit of test data. Compared to uncompressed test data, if there is a bit flip in the compressed data, the codeword may change and hence the decompressed data will have a large number of bit deviation. This deviation in bits can severely degrade the test quality and overall fault coverage which may affect yield. The error resilience is the capability of the test data to resist against such bit flips. Here in this paper, the earlier methods of error resilience is compared and a Hamming code based error resilience technique is proposed to improve the error resilience capacity of compressed test data. This method is applied on Huffman code based compressed test data of widely used ISCAS benchmark circuits. The fault coverage measurement results show the effectiveness of the proposed method. The basic goal here is to survey the effect of bit flips on fault coverage and prepare a platform for further development in this avenue.