A Stastical Test Data Compression Technique with Adaptive Bit Filling and AI Based Reordering: Optimization for Compression and Scan Power

Abstract

Test power and test time have been the major issues for current scenario of VLSI testing. The hidden structure of IP cores in SoC has further exacerbated these problems. The test data compression is the well known method used to reduce the test time. The don’t care bit filling method and test vector reordering method can be used for effective test data compression as well as reduction in scan power. In this paper, in beginning, the mixed approach adaptive algorithm for don’t care bit filling is proposed which is developed to enhance both parameters i.e. the power reduction and compression ratio. After the bit filling, the vectors are reordered using Artificial Intelligence approach. The quality parameter used for reordering is Adaptive Weighted Transition Matrix (AWTM) considering both, scan-in-&-scan-out vectors. The modified selective Huffman coding is applied on the reordered vector set to give the optimum compression. The experimental results on ISCAS benchmark circuit proves that the proposed method gives the better compression as well as better power reduction.