Low Power Testing Architecture in Built-in Self Test

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DC Field	Value	Language
dc.contributor.author	Parmar, Harikrishna	-
dc.contributor.author	Mehta, Usha	-
dc.date.accessioned	2015-10-15T05:21:26Z	-
dc.date.available	2015-10-15T05:21:26Z	-
dc.date.issued	2010-12-09	-
dc.identifier.citation	1st International Conference on Current Trends in Technology, NUiCONE 2010, December 9-11, 2010, Institute of Technology, Nirma University, Ahmedabad	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/6371	-
dc.description.abstract	Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. So test power has been major big concern in large System-on-Chip designs from last decade. In this review paper, Several architecture have been proposed for reducing power dissipation during BIST. The paper contains the detailed survey on various power reduction techniques proposed for scan architecture.	en_US
dc.publisher	Institute of Technology, Nirma University & IEEE	en_US
dc.relation.ispartofseries	ITFEC010-26;	-
dc.subject	Scan Matrix	en_US
dc.subject	Low Power Testing	en_US
dc.subject	BIST	en_US
dc.subject	ATE	en_US
dc.subject	EC Faculty Paper	en_US
dc.subject	Faculty Paper	en_US
dc.subject	ITFEC010	en_US
dc.title	Low Power Testing Architecture in Built-in Self Test	en_US
dc.type	Faculty Papers	en_US
Appears in Collections:	Faculty Papers, EC

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