Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6373
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dc.contributor.authorMehta, Usha-
dc.date.accessioned2015-10-15T05:37:42Z-
dc.date.available2015-10-15T05:37:42Z-
dc.date.issued2010-06-
dc.identifier.urihttp://hdl.handle.net/123456789/6373-
dc.descriptionNirma Universitty Journal Of Engineering And Technology, Vol.1 (1), Jan - Jun, 2010, Page No. 38 - 41en_US
dc.description.abstractIt has been seen that the test data compression has been an emerging need of VLSI field and hence the hot topic of research for last decade. Still there is a great need and scope for further reduction in test data volume. This reduction may be lossy for output side test data but must be lossless for input side test data. This paper summarizes the different methods applied for lossless compression of the input side test data, starting with simple code based methods to combined/hybrid methods. The basic goal here is to prepare survey on current methodologies applied for test data compression and prepare a platform for further development in this avenue.en_US
dc.publisherNirma Universityen_US
dc.relation.ispartofseriesITFEC010-28;-
dc.subjectVLSIen_US
dc.subjectTestingen_US
dc.subjectData Compressionen_US
dc.subjectEC Faculty Paperen_US
dc.subjectFaculty Paperen_US
dc.subjectITFEC010en_US
dc.titleSurvey of VLSI Test Data Compression Methodsen_US
dc.typeFaculty Papersen_US
Appears in Collections:Faculty Papers, EC

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