Back End Netlist Generation and Updation

Abstract

The project 'BackEnd Netlist Generation and Updation' is part of Backend Compiler in which a compiler/Memory is automated. In times, Memory for SOC is developed based upon specific requirement from the client. The Memory, so automated, is tested against the requirement of the client using Netlist file. Netlist file is a text only readable file that depicts the hierarchy of circuits that forms a whole memory. This file, too, determines the interconnection of pins and ports from various circuitry. Testing and generation of Netlist file comes under CDL view. Thus in order to provide client with correct and dynamic memory, Netlist file is assisting the needful.