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DC Field | Value | Language |
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dc.contributor.author | Jani, Rushiraj | - |
dc.date.accessioned | 2016-07-30T05:15:05Z | - |
dc.date.available | 2016-07-30T05:15:05Z | - |
dc.date.issued | 2016-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/6794 | - |
dc.description.abstract | Multilevel inverter topologies are mainly used for high power medium voltage applications. Recently many such inverter topologies are proposed. Due to various inherent advantages like low blocking voltage requirement of the switching devices, reduced harmonic distortion in the output voltage and reduced switching losses, multilevel topologies of inverters widely used in high power induction motor drives. Different levels of pole voltages in multilevel topologies can be obtained by various topologies, but among them, Neutral Point Clamped (NPC), Flying Capacitor (FC) and cascaded H bridge topologies are widely used. Also there are many controlling schemes proposed for such type of inverters, but Sine Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) is most preferred controlling strategies for the Multilevel Inverter in high power medium voltage Induction machine drive system. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 14MEEP10; | - |
dc.subject | Electrical 2014 | en_US |
dc.subject | Project Report 2014 | en_US |
dc.subject | Electrical Project Report | en_US |
dc.subject | Project Report | en_US |
dc.subject | EE (PEMD) | en_US |
dc.subject | Power Electronics, Machines & Drives | en_US |
dc.subject | 14MEE | en_US |
dc.subject | 14MEEP | en_US |
dc.subject | 14MEEP10 | en_US |
dc.subject | PEMD | en_US |
dc.subject | PEMD 2014 | en_US |
dc.title | Design and Implementation of Five Level Inverter | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EE (PEMD) |
Files in This Item:
File | Description | Size | Format | |
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14MEEP10.pdf | 14MEEP10 | 2.31 MB | Adobe PDF | ![]() View/Open |
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