Implementation of Close-Loop Control of Five-Level Neutral-Point Clamped Inverter for DC-link Capacitor Voltage Balancing

Abstract

Induction motors (IM) are the workhorse of the industries. Multilevel inverter (MLI) are mostly preferred for high-power medium-voltage drives, due to its advantages with increase in voltage level, rating of power semiconductor devices, switching fre- quency and the harmonic content in an inverter output voltage waveform reduces. From family of MLI, neutral point-clamped (NPC) inverter are mostly preferred due to its inherent advantages. Many modulation techniques have been developed to cater the growing number of multilevel inverter topologies, from these avail- able modulation techniques, carrier-based pulse width modulation (CBPWM) are mostly preferred due to their simplicity, exibility and reduced computational re- quirements compared to SVPWM technique. Here for switching five-level NPC in- verter phase disposition pulse width modulation (PDPWM) technique is used from various available CBPWM techniques. NPC mainly have one problem of uctuating neutral-point potential (NPP), which leads to severe problem like increase in total harmonics distortion (THD) and increase in voltage stress of the power semiconduc- tor switches. This thesis is focused on balancing of the neutral-point potential which means to balance the voltage across DC-link capacitors by just modifying the modulation technique without any extra hardware. In proposed technique information of ca- pacitor voltages is required only. Capacitor voltages are measured and a band is set and capacitor voltage is allowed to vary between that band by providing offset in individual carrier wave and hence discrepancy in capacitor voltages will reduce. When capacitor voltage touches upper band, the offset which will discharge the ca- pacitor and bring the voltage back within the band is provided and when capacitor voltage touches lower band, the offset which will charge the capacitor and bring the voltage back within the band is provided. Proposed control technique is verified in simulation for 5 hp squirrel-cage induction motor for entire range of modulation index with V/f control. However, the limitation of this control scheme is the fun- damental output voltage of an inverter is not as per the requirement. The output voltage has full dc-link voltage but waveform has only three-levels when machine is operated in five-level. Harmonic contain in output voltage is increase compared to conventional output as offset provision is not in synchronism with reference signal. As level are reduced, dv/dt is increased, which leads to increase in stress on power semiconductor switches, DC-link capacitors, insulation of winding of machine etc. Same results obtained by continuously monitoring and regulating error in capacitor voltages by use of PI controller. For experimental verification of proposed technique hardware prototype of three-phase five-level NPC was developed. dSPACE is used for control and monitoring of close-loop control of proposed technique. Same results are obtained in experimental testing. For testing three-phase star connected 100! resistor is used as load.