Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6842
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dc.contributor.authorVanapariya, Jaydeep-
dc.date.accessioned2016-08-08T08:47:41Z-
dc.date.available2016-08-08T08:47:41Z-
dc.date.issued2016-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/6842-
dc.description.abstractAn inverter is a device which converts the dc power to the ac power to supply it to various ac loads. High power with lower voltage and current ripple can only be catered by multilevel inverters. Multilevel inverter has advantage of lesser har- monics at output side, ability to control reactive power ow, quality output voltage, limitation of device stress, these prose cannot be su ced by two-level inverters so that three-level inverters are having market interest in recent era. Three-level T-type inverter has positive aspects of Two-level inverter such as reduced no of devices, low conduction losses, simple operation with the advantage of Three-level inverters such as low switching losses and superior output quality. Sometimes application needs higher power which cannot be supplied by single inverter unit, there in need of par- allel operation of inverter rises. A zero sequence circulating current(ZSCC) ows between inverters due to their switching state difference mainly which causes cur- rent discrepancy, current waveform distortion, power loss and heating of devices. In this project,the ZSCC paths in parallel network of 3LT2I are analysed, and based on that, various ZSCC inhibition techniques(Carrier synchronization, Zdq control, DC bus Mid point sharing and filter modification) are simulated in Psim simulation tool. Triangular carriers are generated separately for run time modification of various parameters and device characteristics are feeded to emulate the behaviour of actual IGBT. It is found out that Triangular(Carrier) synchronization method reduces the ZSCC current ow between inverters in present system. Experimental results also verifies the stated method with reduction of ZSCC ow from 64A to 1A at 10% of current reference.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries14MEEP29;-
dc.subjectElectrical 2014en_US
dc.subjectProject Report 2014en_US
dc.subjectElectrical Project Reporten_US
dc.subjectProject Reporten_US
dc.subjectEE (PEMD)en_US
dc.subjectPower Electronics, Machines  & Drivesen_US
dc.subject14MEEen_US
dc.subject14MEEPen_US
dc.subject14MEEP29en_US
dc.subjectPEMDen_US
dc.subjectPEMD 2014en_US
dc.titleAnalysis and Elimination of the Circulating Current Flow in Parallel Operation of 3 Level T-Type Grid Connected Invertersen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EE (PEMD)

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