Power Integrity Analysis and Automation of PDN Optimization

Abstract

As more than two billions of transistors are integrated on same die with clock frequencies well above several gigahertz. Because of this, device noise has become the primarily concern for digital ICs relatively which is traditionally considered to be relatively immune from the noise. So, at high frequency, noise is not negligible for digital ICs. Specifically, switching noise i.e power/ground noise has become a primary design criterion for both mixed-signal and high performance synchronous digital ICs. Therefore, power integrity has become the major issue which should be addressed at the system level considering the parasitic effect on package and board. Generally, from a system perseptive, Power Integrity was not considered by the circuit, package and board designers, but if chip does not meet the PI and EMC requirement then the circuit has to be re-designed with a dramatic increase in terms of NRE costs, and subsequent delay in the product chain, thus missing critical time-to-market windows. So, with the customer’s requirement and an increasingly aggressive competition in the market leads to deploy an effective and reusable solutions for a wide range of applications, an accurate and practical modelling approach for the system PDN to estimate the power integrity and EMC behavior before fabrication, and the development of an overall PI/EMC-aware design methodology. In this work, a die, package and board modeling and co-simulation methodology is presented which can be seamlessly integrated into the standard design flow. So, system is breakdown into the multiple components and system level modelling is done for each components to observe the individual performance of this components. Then system level response can be seen by combining them together. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins.As setup is done manually by user in EDA tools which takes sufficient amount of time. So, to reduce the setup time, tools are automated for performing certain task.