Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6865
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPatel, Zinal-
dc.date.accessioned2016-08-12T06:59:09Z-
dc.date.available2016-08-12T06:59:09Z-
dc.date.issued2016-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/6865-
dc.description.abstractInput/Output (I/O) is designed as a component which interface internal core signal to external chip signal. It provides essential bridge between on chip and off chip environment to communicate. Signal which arrives from off chip device has to be verified by the I/O for any incongruity in its deportment other than the defined for the on chip, thus it is very important to design and implement good I/Os. The function of the I/O is to find that from which characteristic of the signal the core can get harm and damage. As part of the solution it also improves the signal or simply rejects it and gives the acknowledgment signal back to the circuits. Thus I/Os are superintend for genuine functioning of the whole chip guards to the core or from the core. However as efficient as core design may be, but at the end it is the I/O which determine the actual efficiency of the chip. And validation of these I/Os are as much as important as its designing.It is imperative for the designer to examine the I/O which was designed under the divergent practical conditions. In the verifications deriving strength of the chip, delay in signal, power etc. are taken care as they all are deliberately based on the I/O. At the time of I/O verification it is more important rather than whether the core is compliant with the specifications given by the designer or not because even a small difference in the behavior of the I/O may damage the entire circuit or can create problems to the off chip environment circuit. It is the liability of the I/O to limit the outgoing signal in all respect like amplitude, frequency, delay etc. under the specified specification parameters by the designer.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries14MECC14;-
dc.subjectEC 2014en_US
dc.subjectProject Reporten_US
dc.subjectProject Report 2014en_US
dc.subjectEC Project Reporten_US
dc.subjectEC (Communication)en_US
dc.subjectCommunicationen_US
dc.subjectCommunication 2014en_US
dc.subject14MECCen_US
dc.subject14MECC14en_US
dc.titleAnalysis And Simulations In ADE L/XL Up to Pre-Post Layout With Ocean Scripting For Mismatch And SIPI Setupsen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (Communication)

Files in This Item:
File Description SizeFormat 
14MECC14.pdf14MECC144.81 MBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.