Standard Cell Characterization And Packaging

Abstract

Standard library cells are basic building blocks for ASIC (Application-Specific Integrated Circuit) design. They lower design complexity through the use of predesigned and pre-characterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. Cell Characterization is the process of simulating a standard cell with a spice simulator (like ELDO) and an automated characterization tool to extract this information and convert into a format that other tools can utilize.Using SPICE simulator timing, power and noise information is extracted for each cell. All this data has to be consolidated in a library (in Synopsys Technology Format) along with some important views and documentation in form of a package. This product (package) is then used by designers for designing ASIC chips. The libraries are used by synthesis tools for extracting gate level netlist of the digital circuit from RTL level design and these are also used in place and route tools. In the initial phase of my dissertation work, explain the working of tools (like ELDO, etc.) and the ow for characterization and packaging.Also describe the methodologies used to evaluate timing, power, constraints and noise parameters. In the second phase, standard cell characterization and packaging was done for nanometer Technology designs. The prime focus of this work is firstly to characterize (extract timing, power, noise information) set of standard cells (nanometer designs) at various PVT (Process, Voltage, Temperature) corners provided by the customer for a fixed set of input slopes and load capacitances and secondly, to consolidate the characterized data of each cell in a .lib (library) also including some important views (Back end, front end, packaging, etc.) in a package that is later used by SoC designers.