Development of A Verification Methodology to Verify SRAM Models Using SV-UVM

Abstract

To verify different kind of memories, different verification environment are being developed which is time consuming process.These memories are hard macros which are deliver to customer in different views and used them at SOC level design. As all the views of the IP have to be extensively verified to make all the views align with the IP's specifications before releasing it out.This verification should be done in functional way as well as in terms of timing also, As set up and hold violations are being performed big part at pico seconds also. Using System Verilog and UVM methodology, a manageable and reusable verification environment can be developed which is based on higher abstraction level. This methodology gives greater edibility for generating constrained random stimuli which is very much required to cover the maximum design space. This project develop a generic verification environment using System Verilog and UVM methodology, which is targeted for the verification of different kinds of memories such as ROM, SRAM Single port and Dual port in functional as well as timing constraints having its own features and Architectures.