Testchip Validation Automation

Abstract

As the technology tends to continuously shrink from small scale integration (SSI) to very large scale integration (VLSI), design for testability is also included more seriously into the ASIC flow. With increase in complex system, testability is an increasing concern in almost every application and in every area of application development.Test engineers put more efforts in addressing the issue of testability at the device, board, and system levels deliver more consistently reliable and cost effective products to the market place. This means building test capabilities in every phase of development and deployment, including design verification, hardware and software integration. Also, ICs are made through block production, therefore, it is necessary to test them before actual manufacturing so as to reduce cost of manufacturing. The aim of test pattern validation tool is to reduce total cycle time of test cases validation. Pattern validation environment is useful to launch various test cases in order to verify characteristics of Testchip SoC which consists of subsystems like memory block, standard cell block. For reliable and efficient testing, the tool needs to work fast and for every possible testcase, without fail and it is the utmost priority of the design engineer. Standard cell block design tool is used to test the standard cell libraries for different types of cells for their functionality and delays in various possible PVT (process, voltage and temperature) corners. The libraries that need same inputs from input are better to be combined so that the tool can work faster. This control, whether to combine libraries or not, should be with the user or tester. This feature adds on to the efficiency of the tool. There has been sufficient rise in the number of critical paths in digital designs due to gradually shrinking CMOS. Conventional techniques for evaluation of digital design have reduced the gap between CAD and Si design. But these technologies are restrained to limited process, voltage and temperature (PVT) corners and consumes a lot of time. The solution is presented by the CAD correction factor tool. Distribution request tracker reporting tool is used to get the details of the products that has been requested earlier from the database, through web service. This reporting from the database should be as fast as possible. Therefore, there was a need for optimization of the tool to make it work faster and accurate.