FPGA Based Development Board Design & Characterization of CDR of HSSL

Abstract

The project is about creating an FPGA development board targeting multiple applications like creating a validation platform for data converters, making a platform for characterizing the receiver system of high speed serial link, generation of jittery data in FPGA and much more. The first phase of the project was to do the feasibility analysis which includes device selection analysis, IO selection analysis for maximum data rate support, selection of other resources of an FPGA board compatible with the selected FPGA and do the power analysis. While the board is under fabrication process, the targeted applications were developed and implemented using other FPGA devices available in the laboratory. The applications include: (1) Characterization of ASIC based CDR unit on an FPGA based BER Test Platform (2) Generation of jittery data using FPGA for reducing the cost of instruments used to generate jitter. (3) The use of ChipScope Pro for debugging the design implemented in FPGA. The tools used till now to serve the above mentioned purposes are Xilinx ISE (XST, RTL & Technology Map view, Place & Route, PlanAhead, ChipScope Pro, ISim), ModelSim, VIVADO, Keysight ADS, Synopsys Synplify Premier; FPGAs used are Virtex-4, Virtex- 6, Virtex-7, Spartan-6, Artix-7, Zynq7000 and the instruments used are Vector Network Analyzer, Logic Analyzer and Mixed Signal Oscilloscope.