Frontend Automation of the Verification Tasks for Set-top Box SoCs and backend Automation / Verification for Standard cell Libraries

Abstract

Interrupt plays an important role while connectivity check and a mechanism is re- quired where this interrupt connectivity can be checked while bringing up the SoC also to incorporate way to handle any changes happening in interrupt by directly using interrupt connectivity specification. Along with this also, there is need to be taken care of any auto generation, execution and result reporting of test cases. In first automation, the test cases generation which needs to be run to check the connectivity of the signals available on the pins of modules in SoC is automated. To check the connectivity, hierarchy of all the signals are extracted from the input files. After that, one more script is developed to automate runs of testcase for all modules by taking previous hierarchy files as input and also stored the results of test in database. Thus testcase generation, execution and result reporting is automated. While debugging any signal in RTL in NCSim simulator, it is required to have knowledge about how to fetch variable definition and its value from specification. It takes time if it is done manually for each value of addresses. In second automation, a script is developed to extract variable names from specification files automatically and create a .tcl file for all the variables. After creating .tcl file for all variables, that file is attached to the NCSim simulator in mnemonic maps and then applied mapping on the waveform to display variable name in place of its address. By this automation, debugging will become easy, quick and more accurate. For any layout design validation, DRC are different for different technologies. So if it is possible to use one validation scenario which can be used for all type of tech- nologies with minor changes then validation will become easy and faster. In third automation, developing an SVRF based standard cell specific rule procedure to run rule check for layout design through caliber in virtuoso for universal validation of different technologies like 28 nm and 40 nm technology.