An Effective and Effectual approach of SDC Management at SoC

Abstract

Todays SoC is witnessing an increasing number of blocks and complexities. Management and timing closure of these blocks is becoming a highly diverse and serpentine task. However a swift and meticulous timing analysis is also a mandate. Standard Design Constraints (SDC) is used to provide the timing constraints for the design under analysis. This includes specification of constraints under which the Timing analysis must take place. Promotion and Demotion are done to check the proper positioning of constraints in the design. The major challenge to do the correct timing analysis is to have an accurate SDC. SDC development depends on top constraints, DFT constraints as well as IP constraints. The prime challenge is to collect all these inputs and develop accurate SDC for top SOC as well as for underlying Partitioned Units (PU). The process of upgrading the IP level constraints to SoC level is termed as promotion. Similarly, the process involving downgrading the SoC level constraints to their constituent IP level is called demotion. The effective Promotion/Demotion depends on the effectiveness of the applied SDC. So it is necessary to pass correct SDC during promotion and demotion. To make the SDC management more effective and efficient we are appending three different techniques to precisely manage the complete SDC in SOC development process. This work proposes a methodology that enables constraints management of SOC and Partitioned units (PU). The three approaches include filtering of IPs SDC, XLSto- CLOCK and Promotion/Demotions of SDCs. The filter approach cleans the IPs SDC to generate top SDCs for top level timing analysis. XLS-to-Clock approach generates the correct SDCs for generated clock while Promotion/Demotion will help to generate the SDCs of top SOC and Partitioned Units (PU). This methodology is verified on setup box SOCs and result indicate clean timing analysis in first iteration itself.