ARMv8M ACK Tests on Cortex-M7 and Reference Testbench

Abstract

Test issues in Architecture Compliance Kit of v8M architecture (ACKv8M) product when run on a Partner specific RTL world can be present. The Partner specific RTL could have additional micro-architectural features like Out-of-order execution, Dual issue, Random wait states, Store buffers, etc. These micro architectural features cannot be tested in the model used by ACKv8M product. In order to catch the test issues in ACKv8M product before reaching to partner, a stabilized core in market which has all these micro-architectural features are taken for this exercise. Since Cortex-M7 is the stabilized core in the market for ARMv7M profile, Cortex-M7 is chosen for ACKv8M test. Final goal accomplished by first integrated latest released Unified Testbench (UTB) with Cortex-M7’s top level testbench and overcome all the mismatches between top level testbench and UTB. Basic RIS INT suite test on Cortex-M7 is to verify the random instruction sequence generated by tool and its ran on Corex-M7. Results are generated for v8M-ACK tests with and without micro-architectural features. From results analysis of failure and validation of failures are confirmed as architecture difference between v7M and v8M. The Reference Testbench is a part of ACK environment on which trickbox components are implemented which are more complex in implementation as well as on coding side. To verify these each trickbox components individually block level testing on these components are done. With the help of block level testing overall quality as well bugs present into trickbox components are resolved.