ARM CPU Verification Methodologies

Abstract

Main aim of this project is to do support work for various ARM CPU verification methodologies. This project includes scripting work, C programming work and assembly test writing work to evaluate certain ARM architecture features. Team is only concern with Final Id that is made of sub id, test name and context name, so YAML parser is a perl script that is used to parse specific filed to make Final Id. Like .exe file we can not open .ELF file so ELF parser is a C program to read all values from ELF Header Table, Section Header Table and Program Header Table and to print them. With the help of this ELF parser code merging of ELF is achieved. ELF parser code is used to merge 200 ELF at one time. This Final merged ELF is used in Self Modifying Code to run each ELF at run-time. Self Modifying Code tests are written in assembly language with the help of A64 and A32 instruction set. These codes are used to alter the flow of execution at run time. Self Modifying test code loads a merged ELF at run-time and execute them. The runtime flow of ELF is used to check different aspect like virtual aliasing and cache invalidation. There are three types of verification methodologies: AVS, DVS and RIS. In AVS methodology, number of self written assembly test are made to run on ARMarchitecture to verify its behaviour. Debugging of failed test, report analysis, various comparison report with different hardware, final pass rate analysis and skipp test analysis come under AVS verification methodology.