Clock Data Derate And On Chip Setup Improvement In Silicon

Abstract

In lower technology node, to predict an exact delay is a bit difficult because of different types of on chip variations. These on chip variations occur due to mask alignment, etching process etc. We need to keep some margin in which delay can be changed. If this margin is very high, then it is difficult to achieve targeted fre- quency and if the margin is very low then it may cause function failure. This margin is called as De-Rate Factor. Generally derate factor is a constant which is given by significant team. Advancement in De-Rate factor results in Advanced On Chip Varia- tion (AOCV) and Parameterized On Chip Variation (POCV). De-Rate Factor can accurately be known by considering di erent types of varia- tions. The circuit is made such that we can detect effect of both systematic and random variations so that we can get derate factor considering all types of variations. Virtuoso schematic editor is used to make circuit and simulations are done by eldo simulator by which we can extract information also to calculate exact delay. The cir- cuit made is inspired by some previous results and some papers regarding variability. Characterization is a process to get exact delay from one op to another op. Here both clock path and data path needs to be characterized so as to get exact delay when intentionally we fail setup or hold so that we come to know by what factor delay changed on various PVT corners. Setup and hold time of ops also plays an important role in chip designing as we must handle setup and hold violations to meet timing requirements. At pre-CTS we can execute macro model for setup improve- ment such as at CTS tool already knows that by this much delay should be added more at this path to meet timing requirements. In this project, we implemented the design to find derate factor. Gradually increasing frequency in design will fail the setup and at that time we will compare the clock and data path delay on both CAD and Si, which will decide how much derate should be applied to standard cells.