Circuit Simulation/Reliability Verification TPT and Efficiency Improvements in Tool/flow For Analog And Memory Ips

Abstract

Design of Low Power Analog Integrated Circuits on leading edge process technologies poses a significant challenge due to a number of parameters like process variation and design complexities. Faster TTM(Time to Market) is very important to deliver IPs with quality in timely manner. CAD team is continuously striving to come up with new and innovative solutions that help achieve faster TTM with quality. Tool and flow improvement is a part of this study with focus on to reduce complete verification cycle and to improve designer’s productivity. The focus of this project is to improve circuit simulation and verification flow efficiency in addition to reliability verification. This involves understanding current circuit simulation and verification process and work closely with the design teams to study and identify the inefficiencies and long poles first. Following this, a deep dive analysis will be done to identify the inefficiencies clearly and action plan to address them. This involves a detailed study on various EDA simulator solutions available along with their evaluation, bench marking from deployment perspective. This involves several experiments and tool/flow studies with end goal of coming up with most optimal method which yields highest ROI. This also involves building verification framework that can focus on quality checks of the IPs and tools and flows to improve overall support bandwidth spend by CAD team. At the same time, focus is on streamlining only the needed checks and eliminate any redundant checks. The focus will be on functional simulations, power analysis, device reliability, interconnect RV to maintain design sanity as part of this study.