Physical Implementation of High Speed Serial Interface

Abstract

The processing speed of the single chip today has increased drastically since the beginning of the IC technology. The interconnection bandwidth is the factor which is degrading the performance of the digital system so our target is to achieve higher off chip data rate by applying different manipulation in placement and routing of the design. The high speed serial interface is implemented at the physical layer and our focus area is to implement the complete flow from RTL (Register Transfer Logic) to GDS (Graphic Database System) of this interface. The speed of this interface is in the range of few tens of Gbps. The synthesized gate level netlist is generated from the RTL which also has the influence of physical constraints and timing constraints. Formal Verification is carried out to ensure logical equivalency between different abstraction levels. Auto Place and Route (APR) is implemented on synthesized netlist with physical constraints and timing constraints keeping in mind. First placement is exercised with physical constraints, then Clock Tree Synthesis (CTS) and Routing is implemented bounded by timing constraints such that slack is balanced. After routing, the parasitic report is given for PV (Performance Verification) to close the timing violation. LVS (Layout vs. Schematic) and DRC (Design Rule Check) cleanups are done to ensure manufacturability. RV (Reliability Verification) checks for the IR drops and Electromigration issues. After cleaning up all these physical verification flows the final GDS file is given for fabrication. This implementation is carried out at the submicron technology node below 50 nm.