Evaluation And Deployment Of Standalone Memory Characterization

Abstract

Nowadays, embedded CMOS memories are more and more used in system-on-chip (SoC) solutions. Chip designers need a large CMOS memory offer in terms of memory types, aspect ratios, features etc. The performance of memory play major role in ASIC design. Therefore characterization of memory in terms of timing, power and capacitor is very crucial for SoC. Increase in design complexity and reduction in chip size created necessity of good memory characterization. Faster memory development can be possible with good memory IP designing and characterization. Memory compilers are used for faster memory characterization. They are used to generate models for memory from few known instances. For advance memory modeling improving accuracy of memory model is striving. Automated memory models generation with high-throughput for large range of PVT is hard to achieve. Typically 70% of engineering effort and time for memory characterization is focused on timing analysis and model generation. To reduce simulation without reducing much accuracy is much of concern for characterization engineer. One methodology to reduce the number of memory instances for SPICE simulations is proposed in this thesis, without sacrificing much of SPICE inaccuracy. CCS Noise is a new advanced current-based driver model that enables accurate noise analysis with results very close to SPICE simulation. It not only precisely models injected crosstalk noise bumps, but also allows more advanced analysis, such as propagated noise bumps and the driver weakening, without significant characterization effort. Implementation method for CCS noise view is described in this thesis.