Impact of Micro-Architectural Optimizations on Post Layout Power

Abstract

Power consumption is one of the top concerns of Very Large Scale Integration (VLSI) circuit design, for which Complementary Metal Oxide Semiconductor (CMOS) is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, and thus designers are required to choose appropriate techniques that satisfy application and product needs.[1] In general, low power VLSI Design can be achieved at all levels of the VLSI Design (system, algorithm, architecture, circuit, logic, device,& technology levels). But optimizations for low power VLSI Design done at higher abstraction results in comparatively higher power savings. This report presents implementation of Shift Register to Circular Buffer MicroArchitectural optimization for low power VLSI Design. Shift Register to Circular Buffer Micro-Architectural optimization reduces the switching activity of the flops& thus reduces the dynamic power consumption. Circular Buffer is the functional equivalent of the Shift Register with less flops toggling. In Shift Register (Serial In Serial Out) all registers toggle even though only one register is read/written. But Circular Buffer implementation is done such that only one register toggle at any time thus consumes less power. In this work the impact of optimization is analyzed not only on RTL power but also on post layout power. The implementation, overhead& impact of Shift Register to Circular Buffer Micro-Architectural optimization on post layout power is presented in this report.