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Title: | Low Power Static and Dynamic Checks for LTE Modem |
Authors: | Joshi, Harshita |
Keywords: | EC 2014 Project Report Project Report 2014 EC Project Report EC (VLSI) VLSI VLSI 2014 14MEC 14MECV 14MECV07 |
Issue Date: | 1-Jun-2016 |
Publisher: | Institute of Technology |
Series/Report no.: | 14MECV07; |
Abstract: | As the VLSI technology dimensions are shrinking day-by-day, the challenges of higher power consumption and reliability come into picture. To avoid the problems of reliability and device failure due to higher power consumption, it is advisable to use Power Management Architecture. Below 90 nm, power management becomes inevitable. This report describes the main components of power management architecture. With this added power architecture, it is very challenging to completely verify the functionality of the device. This complete verification demands structural checking as well as functional checking. New methodology and tools are needed which can identify and consider the power architecture for verification. For this project, low power static and dynamic checks were carried out at the RTL level. A common standard for specifying power intent called as Unified Power Format is explained in this report. Static checks which verify the structure of the power intent and design, and dynamic checks which verify the functionality of the design along with the added power intent are required. This report describes low power static checks at RTL level. The need for static checks, the static check violations, and the tools used, Spyglass Power and VCStatic Low Power, for their analysis are also described. Low power dynamic checks at RTL level are explained after low power static checks. Tool used for performing dynamic checks, VCSMx by Synopsys, is also explained. The need of low power dynamic checks is explained in detail. Power aware testbench and verification components are described. Several approaches like directed tests, automated script checking and assertion based checking, were used to completely verify the design. These approaches are explained in this report. For both the static and dynamic checks, the bugs found and the issues faced are also explained. Once the static and dynamic checks are bug-free, the design can be signed-off to next stages of implementation. |
URI: | http://hdl.handle.net/123456789/6929 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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14MECV07.pdf | 14MECV07 | 2.47 MB | Adobe PDF | ![]() View/Open |
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