Impact of IEEE 1801 on Design for Testability

Abstract

Hardware Testing is commonly used to check whether faults exist in a digital system. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. To help achieve the power goals while being in accordance with Moore's law, innovations in architecture and design strategies are needed to help curb the increasing power dissipation in circuits. Advanced integration of power reduction techniques with CAD tools and the design flow are necessary to make design of low power circuits as easy as possible with the least manual intervention. The low power techniques used comprehensively today have been integrated with CAD tools, but portability and uniformity details are absent. This report details IEEE standard 1801 - Unified Power Format (UPF) along with its usage to achieve low power consumption. As complexity of designs are increasing day-by-day, designs are becoming power hungry. In order to meet the power requirement of such complex designs various techniques like Multi-Voltage and Block level power turn on and turn off are employed. UPF (IEEE 1801) provides a common platform so that same power information can be used across RTL, Synthesis, and Timing .UPF (IEEE 1801) brings its own implementation challenges and affects multiple stages of ASIC flow, like verification, physical implementation, DFT, etc. Analyzing these impacts introduced by UPF on DFT and providing a recommendation or solution to overcome these impacts are the primary aim of this project.