Verification of IP at SoC level

Abstract

In today's regularly advancing technological world its very important for the manufacturer to achieve a very great quality in the minimum time, in short a good time to market is high on demand. The verification of design enacted makes it a very vital part to ensure the quality of product and to ensure a bug-free design when provided to the customer. Here in thisthesis the main area of focus is to complete a verification flow from RTL[Register TransferLevel] to GLS[Gate Level Simulation] with timing constraints. The synthesized gate levelnet-list is generated, which also has the influence of physical constraints and timing constraints that are generated from RTL. Verification Plan is designed as per the functional equivalency understood from the design. In SoC level most of the IP's come under the category of the Black Box verification, which makes it very vital for the verification engineerto design the flow strictly as per specifications provided by the IP owner. Once the plan is formed thetestcases are developed as per the plan and the IP design constraints, the connectivity with the SoC environment, interconnects and access the core.In this project our aim is to cover a complete verification flow covering all the IPs functionality and other peripherals. Every team member is assigned with the verification ownershipof different IPs that are included in the SoC. I was assigned the ownership of some criticalIPs such as Graphic Engine and Smart Card Interface[SCI]. I had developed a completetest-bench flow stretching from verification plan to RTL verification and finally completing the verification flow at Gate Level.