Extracted Timing Model Generation & IR Drop Analysis at Advance Technology Node

Abstract

For timing analysis and IR Drop analysis, a hierarchical design methodology allows a teamof engineers to collaborate on a single chip. The team creates timing budgets throughout the design, often at the pins of the blocks. Then, team members can close timing on their blocks, independent of top-level analysis, compared to full at analysis; this hierarchical approach is a practical way to manage the size and complexity of today's SOCs. There are different modelling approaches in hierarchical timing analysis that address accuracy concerns. Extracted Timing Models (ETMs) take the form of Liberty models (.lib) and use abstraction to minimize the amount of data while aiming to preserve accuracy. By replacing respective blocks in hierarchical timing analysis, ETM's can speed up analysis quite a bit and also minimize the memory footprint for full-chip analysis. Similarly for IR Drop analysis, Static and dynamic can be done. Static IR Drop analysis done at early stages of design helps to detect hot spot in the design as early as possible so the design can be modified as soon as possible.IR drop analysis done to ensure the proper functioning of chip.