Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6933
Title: Development and Validation of Memory Built In Self Test (MBIST) IP
Authors: Monpara, Dhruvik
Keywords: EC 2014
Project Report
Project Report 2014
EC Project Report
EC (VLSI)
VLSI
VLSI 2014
14MEC
14MECV
14MECV12
Issue Date: 1-Jun-2016
Publisher: Institute of Technology
Series/Report no.: 14MECV12;
Abstract: If you design a product, fabricate and test it, and it fails the test, then there must be a cause for the failure. Either the test was wrong, or the fabrication process was faulty, or the design was incorrect, or the specification had a problem. Anything can go wrong. The role of testing is to detect whether something went wrong and the role of diagnosis is to determine exactly what went wrong, and where the process needs to be altered. Therefore, correctness and effectiveness of testing is most important for quality products (another name for perfect products). A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. The main purpose of BIST is to reduce the complexity, and thereby decrease the cost and reduce reliance upon external (pattern-programmed) test equipment. BIST reduces cost in two ways: reduces test-cycle duration, reduces the complexity of the test/probe setup, by reducing the number of I/O signals that must be driven / examined under tester control. Today’s electronic designs like SOC (system of chip) have 80 to 90\% of memory element in their design. So there is a great need to test and verify these memories in order to have the correct functionality of the designed SOC. The built-in self-test employed for memories are known as MBIST (Memory Built-In Self-Test). Like other BIST logic, MBIST logic is inbuilt within memory only. The MBIST logic may be capable of running several algorithms to verify memory functionality and test for memory faults specifically designed and optimized for these. MBIST also proposed redundancy scheme. Where after testing if fault is present in any row or perticular word than that row or word is replaced by redundant row or word. This scheme needs BIRA (Built in redundandancy Analysis) module and BISR (Built in Self Repair) module.
URI: http://hdl.handle.net/123456789/6933
Appears in Collections:Dissertation, EC (VLSI)

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