Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6935
Title: Design Verification and Gate Level Power Analysis of Turbo Decoder
Authors: Patel, Axay
Keywords: EC 2014
Project Report
Project Report 2014
EC Project Report
EC (VLSI)
VLSI
VLSI 2014
14MEC
14MECV
14MECV14
Issue Date: 1-Jun-2016
Publisher: Institute of Technology
Series/Report no.: 14MECV14;
Abstract: A channel decoding plays important role to remove noise interference from upcoming bit sequence from noisy channel. There exist various algorithms to decode encoded sequence at receiver end. Each algorithm preserves different efficiencies. MaxlogApp (MAP) algorithm has been proven one of the high efficient algorithms for decoding. In turbo decoder, Turbo codes are generated by turbo encoder at transmitter end, having capability of reaching shannonian prediction. Using MAP to decode turbo codes makes one efficient and complex system in modem SOC design. Verification of such design, offers big challenges. Test bench of turbo decoder is already available in open verification methodology. New specification demands, updates in verification plan and test bench. Coverage goal and Functional coverage should be defined efficiently. Turbo decoder can be used in three modes 2G, 3G and LTE. Each mode has different input methods, so to check the correct functionality of each mode; reference model has been developed and modified according to specification. Test bench, reference model and functional coverage have been made generic against some changes in specification. Code coverage and functional coverage is the measure of our effort requires verifying the design. System Verilog covergroups are developed for the turbo decoder design to define the intent of our functional coverage plan. Code coverage and functional coverage reports are generated and analyzed to improve our verification plan. Gate level power analysis offers higher accuracy over RTL power analysis. Gate level power analysis has been carried out for the same design to measure accurate power in the early stage of development. The more accurate power is generated for the clock tree network by estimating first order clock tree using physical library and technology library. Accuracy of the switching activity input is very important for power analysis, so various methods are adopted to generate accurate SAIF file to achieve accurate power. New trends of IoT (Internet of Things) demands the modification of LTE specification, which offers the low cost, more connectivity, long battery life and more applications. New specification of LTE for IoT known as LTE-M is under development to satisfy above demands has been analyzed lightly in the thesis.
URI: http://hdl.handle.net/123456789/6935
Appears in Collections:Dissertation, EC (VLSI)

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