Methodology of RTL Power Analysis for modules on System-on-Chip (SoC)

Abstract

Low Power technology has become popular due to the increasing trend of portable applications available in the market. In the past few years design approach for complex SoC has changed to a great extent. Power, Performance and Area have always been the design constraints for IC designers with power gaining utmost importance in low power applications. Various methodologies like design reuse and design IP are being adopted for complex SoC applications. Early Power Analysis at RTL Design stage thus become important to ensure Power consumption does not cross the Power budget. My team in Broadcom is working on design and verification of Low Power LTE Modem based SoC application. Power Analysis of all blocks on Modem IP is being carried out using PowerArtist tool from Ansys. Power Analysis flow at RTL level for various blocks on SoC has been described in this thesis. Methodology adopted for Power Analysis at RTL development stage differs greatly from gate-level in terms of accuracy, power analysis iteration time and power reduction opportunities. For large design, time required for Power Analysis at gate-level would be very high with very high accuracy as design would be in final stage with timing analysis. But Power reduction opportunities would be very less post-synthesis and also time to market has to be taken care. Thus, Power Analysis approach at RTL level using PowerArtist (Design for Power) tool which incorporates PACE (PowerArtist Calibrator and Estimator) technology has been adopted. PACE technology, which creates a feedback loop between physical and RTL design processes to help ensure accuracy and consistency of RTL power estimates. PACE looks at key design elements, such as clock tree topology, wire capacitance and cell selection distributions, to create design and technology aware models. Average Power Analysis for complex SoC helps to debug power hotspots in design. Average Power Analysis with RTL simulation approach has been described in detail in this thesis. Thesis comprises of importance and necessity of RTL Power Analysis for Low Power applications. RTL Power Analysis methodology adopted and implemented using PowerArtist tool alongwith the tool architecture is described in depth in the thesis. Inputs required to be given to PowerArtist tool for RTL Power Analysis of blocks/modules on SoC includes RTL Design (HDL in VHDL/Verilog), Fast Signal Database (FSDB) file generated using RTL simulation, Clock constraints, Physical libraries of Standard cells and Macros (.lib), Power constarints(UPF/CPF) etc. RTL Power analysis methodology described in this thesis depends on the testcase selected for simulation of RTL design, technology specific physical libraries for standard cells and macros (indicating leakage and internal power for various operating conditions and input pin values), wireload model used for interconnect resistance and capacitance modeling and time interval selected for Power estimation in FSDB file.