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DC Field | Value | Language |
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dc.contributor.author | Patel, Maitri | - |
dc.date.accessioned | 2016-08-30T08:44:48Z | - |
dc.date.available | 2016-08-30T08:44:48Z | - |
dc.date.issued | 2016-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/6939 | - |
dc.description.abstract | Memory has become an essential part on any chip.The number of memories required on chip depends on its application,but the amount of transistors used for information storage is larger than number of transistors used in logic operations. So to increase the yield of chip it has become necessity to increase the reliability of memory. This report represents two solutions named Memory Repair IP and and Synopsys BIST. “The basic idea of BIST, in its most simple form, is to design a circuit so that the circuit can test itself and determine whether it is ‘good’ or ‘bad’…” Apart from this purpose Synopsys BIST is having so many advantages which has been explained in this report. To store and transfer the repaired information of BIST is performed by Memory Repair IP. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 14MECV18; | - |
dc.subject | EC 2014 | en_US |
dc.subject | Project Report | en_US |
dc.subject | Project Report 2014 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (VLSI) | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2014 | en_US |
dc.subject | 14MEC | en_US |
dc.subject | 14MECV | en_US |
dc.subject | 14MECV18 | en_US |
dc.title | Design And Validation Of Mrepair Ip In 45nm Technology | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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14MECV18.pdf | 14MECV18 | 2.41 MB | Adobe PDF | ![]() View/Open |
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