Methodology Development for Timing Exception Handshake in Hierarchical SOC

Abstract

VLSI technology is utilized for application oriented designs. System on chip (SOC) is proven to be right platform for the same. The complexity of SOC leads to the timing issues to be monitored for the successful operation of the chip. The timing analysis tool observes the parameters such as path definition points, slack value of paths and timing exceptions. The tool assumes that data launched at a path startpoint is captured at the path endpoint by the very next occurrence of a clock edge at the endpoint. For paths that are not intended to operate in this manner, we have to declare those paths as having timing exception. Otherwise, the timing analysis does not match the behavior of the real circuit. When certain paths do not behave as per the default setup/hold conditions, the tool will report them as violation. To avoid this we specify timing exceptions. Timing Exceptions can be defined at any level of hierarchy in a SOC. The SOC sub-blocks today are becoming hybrid in nature. They could be Flat model , Binary model HyperScale, lib model Extracted Timing Model (ETM) or Interface Logic Model (ILM). The Flat model uses netlist and Standard Parasitic Exchange Format (SPEF) to represent design. The HyperScale model takes the advantage of physical hierarchical implementation process by reusing the block-level timing for top-level analysis. In such a scenario, the exceptions need to correctly passed from Top to Bottom and vice-versa. This project aims to study the various configurations and methodologies which can be utilized for such handshake of exceptions. The Flat-Flat and HyperScale-HyperScale models with ETM are utilized for Roll-up and Roll-down handshaking methodologies. The HyperScale Constraint Extraction is utilized to extract Full-chip Flat constraints for HyperScale runs.